SAM7X128_14 Datasheet, PDF (281/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 29-18. TWI Read Operation with Multiple Data Bytes with or without Internal Address
BEGIN
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)
Set the Control register:
- Master enable
TWI_CR = MSEN
Set the Master Mode register:
- Device slave address
- Internal address size (if IADR used)
- Transfer direction bit
Read ==> bit MREAD = 1
Internal address size = 0?
Yes
Start the transfer
TWI_CR = START
Set the internal address
TWI_IADR = address
Read Status register
No
RXRDY = 1?
Yes
Read Receive Holding register (TWI_RHR)
No
Last data to read
but one?
Yes
Stop the transfer
TWI_CR = STOP
Read Status register
No
RXRDY = 1?
Yes
Read Receive Holding register (TWI_RHR)
Read status register
No
TXCOMP = 1?
Yes
END
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
281