SAM7X128_14 Datasheet, PDF (614/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Do not disable a channel before completion of one period of the selected clock.
41.3.6 Real Time Timer (RTT)
41.3.6.1 RTT: Possible Event Loss when Reading RTT_SR
If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the RTT_SR is read, the
corresponding bit might be cleared. This can lead to the loss of this event.
Problem Fix/Workaround:
The software must handle the RTT event as an interrupt and should not poll RTT_SR.
41.3.7 Serial Peripheral Interface (SPI)
41.3.7.1 SPI: Bad tx_ready Behavior when CSAAT = 1 and SCBR = 1
If the SPI2 is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed consecutively on the
same slave with an IDLE state between them, the tx_ready signal does not rise after the second data has been
transferred in the shifter. This can imply for example, that the second data is sent twice.
Problem Fix/Workaround
Do not use the combination CSAAT = 1 and SCBR = 1.
41.3.7.2 SPI: LASTXFER (Last Transfer) Behavior
In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on the data written in the
SPI_TDR when the TX_EMPTY flag is set. If for example, the PDC writes a “1” in the bit 24 (LASTXFER bit) of the
SPI_TDR, the chip select will rise as soon as the TXEMPTY flag is set.
Problem Fix/Workaround
Use the CS in PIO mode when PDC mode is required and CS has to be maintained between transfers.
41.3.7.3 SPI: SPCK Behavior in Master Mode
SPCK pin can toggle out before the first transfer in Master Mode.
Problem Fix/Workaround
In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx registers.
41.3.7.4 SPI: Chip Select and Fixed Mode
In fixed Mode, if a transfer is performed through a PDC on a Chip select different from the Chip select 0, the output
spi_size sampled by the PDC will depend on the field, BITS (Bits per Transfer) of SPI_CSR0 register, whatever the
selected Chip select is. For example, if SPI_CSR0 is configured for a 10-bit transfer whereas SPI_CSR1 is configured for
an 8-bit transfer, when a transfer is performed in Fixed mode through the PDC, on Chip select 1, the transfer will be
considered as a HalfWord transfer.
Problem Fix/Workaround
If a PDC transfer has to be performed in 8 bits, on a Chip select y (y as different from 0), the BITS field of the SPI_CSR0
must be configured in 8 bits, in the same way as the BITS field of the CSRy Register.
41.3.7.5 SPI: Baudrate Set to 1
When Baudrate is set at 1 (i.e. when serial clock frequency equals the system clock frequency) and when the BITS field
of the SPI_CSR register (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15), an
additional pulse will be generated on output SPCK.
Everything is OK if the BITS field equals 8,10,12,14 or 16 and Baudrate = 1.
Problem Fix/Workaround
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
614