SAM7X128_14 Datasheet, PDF (653/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Version
6120F
(Continued) ^Comments
Change
Request
Ref.
DBGU: Corrected references from ice_nreset to Power-on Reset in Figure 26-1 on page 196, Functional
Block Diagram, and in FNTRST bit description in Section 26.5.12 “Debug Unit Force NTRST Register” on 2832
page 218.
PIO:Section 27.4.4 “Output Control” on page 222, typo corrected
Section 27.4.1 “Pull-up Resistor Control” on page 221 reference to resistor value removed.
05-346
05-497
Figure 27-3 on page 221 0 and 1 inverted in the MUX controlled by PIO_MDSR..
3053
04-183
SPI: Section 28.7.5 “SPI Status Register” on page 262 SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR
location defined.
Section 28.7.4 “SPI Transmit Data Register” on page 261, LASTXFER: Last Transfer text added.
05-434
Section 28.7.2 “SPI Mode Register” on page 258, PCSDEC: Chip Select Decode changed.
05-476
Updated Figure 28-1, ”Block Diagram” on page 244, removed Note. Removed bit FDIV from Section 28.7.2 ^05-484
“SPI Mode Register” on page 258 and Section 28.7.9 “SPI Chip Select Register” on page 267. LLB
description modified in Section 28.7.2 “SPI Mode Register” on page 258.
Updated Figure 28-9, ”Slave Mode Functional Block Diagram” on page 255 to remove FLOAD.
Updated information on SPI_RDR in Section 28.6.3 “Master Mode Operations” on page 249. Added
information to SWRST bit description in Section 28.7.1 “SPI Control Register” on page 257. Corrected
equations in DLYBCT bit description, Section 28.7.9 ”SPI Chip Select Register” on page 268.
1542
1543
Changes to Section 28.6.3.8 “Mode Fault Detection” on page 254.
1676
USART:
Manchester Functionality Removed.
2768
Section 30.4 “I/O Lines Description” on page 293, text concerning TXD line added.
Section 30.6.1.3 “Fractional Baud Rate in Asynchronous Mode” on page 297, using USART “functional
mode” changed to USART “normal mode”.
Table 30-3, “Binary and Decimal Values for Di,” on page 298 and Table 30-4, “Binary and Decimal Values
for Fi,” on page 299: DI and Fi properly referenced in titles.
Figure 30-25, ”IrDA Demodulator Operations” on page 314 modified.
Section 30.6.4.1 “ISO7816 Mode Overview” on page 310 clarification of PAR configuration added.
Section 30.6.7 “Modem Mode” on page 316 Control of DTR and RTS output pins.
Table 30-2, “Baud Rate Example (OVER = 0),” on page 296 60k and 70k MHz clock speeds removed.
“Asynchronous Receiver” on page 301 2nd line in 4th paragraph changed.
“Receiver Time-out” on page 306 list of user options rewritten.
1552
1770
2942
3023
Section 30.7.1 ”USART Control Register” STTTO bit function related to TIMEOUT in US_CSR register
Section 30.7.6 ”USART Channel Status Register” TIMEOUT bit function related to STTO in US_CR register
TC: Section 32.5.12 “External Event/Trigger Conditions” on page 388 “....(EEVT = 0), TIOB is no longer
used as an output and the compare register B is not used to generate waveforms and subsequently no
IRQs. Note ⁽¹⁾ attached to ”EEVT: External Event Selection” in Section 32.6.5 “TC Channel Mode Register:
2704
Waveform Mode” on page 395 further clarifies this condition.
PWM: Section 33.5.3.3 ”Changing the Duty Cycle or the Period”: updated info on waveform generation. 1677
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
653