SAM7X128_14 Datasheet, PDF (536/662 Pages) ATMEL Corporation – ARM-based Flash MCU

37.3
Functional Description
The EMAC has several clock domains:

System bus clock (AHB and APB): DMA and register blocks

Transmit clock: transmit block

Receive clock: receive and address checker blocks
The only system constraint is 160 MHz for the system bus clock, above which MDC would toggle at above 2.5 MHz.
The system bus clock must run at least as fast as the receive clock and transmit clock (25 MHz at 100 Mbps, and 2.5
MHz at 10 Mbps).
Figure 37-1 illustrates the different blocks of the EMAC module.
The control registers drive the MDIO interface, setup up DMA activity, start frame transmission and select modes of
operation such as full- or half-duplex.
The receive block checks for valid preamble, FCS, alignment and length, and presents received frames to the address
checking block and DMA interface.
The transmit block takes data from the DMA interface, adds preamble and, if necessary, pad and FCS, and transmits
data according to the CSMA/CD (carrier sense multiple access with collision detect) protocol. The start of transmission is
deferred if CRS (carrier sense) is active.
If COL (collision) becomes active during transmission, a jam sequence is asserted and the transmission is retried after a
random back off. CRS and COL have no effect in full duplex mode.
The DMA block connects to external memory through its ASB bus interface. It contains receive and transmit FIFOs for
buffering frame data. It loads the transmit FIFO and empties the receive FIFO using ASB bus master operations. Receive
data is not sent to memory until the address checking logic has determined that the frame should be copied. Receive or
transmit frames are stored in one or more buffers. Receive buffers have a fixed length of 128 bytes. Transmit buffers
range in length between 0 and 2047 bytes, and up to 128 buffers are permitted per frame. The DMA block manages the
transmit and receive framebuffer queues. These queues can hold multiple frames.
37.3.1 Memory Interface
Frame data is transferred to and from the EMAC through the DMA interface. All transfers are 32-bit words and may be
single accesses or bursts of 2, 3 or 4 words. Burst accesses do not cross sixteen-byte boundaries. Bursts of 4 words are
the default data transfer; single accesses or bursts of less than four words may be used to transfer data at the beginning
or the end of a buffer.
The DMA controller performs six types of operation on the bus. In order of priority, these are:
1. Receive buffer manager write
2. Receive buffer manager read
3. Transmit data DMA read
4. Receive data DMA write
5. Transmit buffer manager read
6. Transmit buffer manager write
37.3.1.1 FIFO
The FIFO depths are 28 bytes and 28 bytes and area function of the system clock speed, memory latency and network
speed.
Data is typically transferred into and out of the FIFOs in bursts of four words. For receive, a bus request is asserted when
the FIFO contains four words and has space for three more. For transmit, a bus request is generated when there is
space for four words, or when there is space for two words if the next transfer is to be only one or two words.
Thus the bus latency must be less than the time it takes to load the FIFO and transmit or receive three words (12 bytes)
of data.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
536