SAM7X128_14 Datasheet, PDF (102/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 19-4. Code Read Optimization in Thumb Mode for FWS = 3
3 Wait State Cycles
3 Wait State Cycles
Master Clock
3 Wait State Cycles
3 Wait State Cycles
ARM Request (16-bit)
Code Fetch
@Byte 0
Flash Access
Buffer (32 bits)
@2 @4
@6 @8
@10 @12
Bytes 0-3
Bytes 4-7
Bytes 0-3
Bytes 8-11
Bytes 4-7
Bytes 12-15
Bytes 8-11
Data To ARM
0-1 2-3
4-5 6-7
8-9 10-11
12-13
Note:
When FWS is equal to 2 or 3, in case of sequential reads, the first access takes FWS cycles, the second access one
cycle, the third access FWS cycles, the fourth access one cycle, etc.
19.2.3 Write Operations
The internal memory area reserved for the embedded Flash can also be written through a write-only latch buffer. Write
operations take into account only the 8 lowest address bits and thus wrap around within the internal memory area
address space and appear to be repeated 1024 times within it.
Write operations can be prevented by programming the Memory Protection Unit of the product.
Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Write operations are performed in the number of wait states equal to the number of wait states for read operations + 1,
except for FWS = 3 (see “MC Flash Mode Register” on page 108).
19.2.4 Flash Commands
The EFC offers a command set to manage programming the memory flash, locking and unlocking lock sectors,
consecutive programming and locking, and full Flash erasing.
Table 19-2. Set of Commands
Command
Write page
Set Lock Bit
Write Page and Lock
Clear Lock Bit
Erase all
Set General-purpose NVM Bit
Clear General-purpose NVM Bit
Set Security Bit
Value
0x01
0x02
0x03
0x04
0x08
0x0B
0x0D
0x0F
Mnemonic
WP
SLB
WPL
CLB
EA
SGPB
CGPB
SSB
To run one of these commands, the field FCMD of the MC_FCR register has to be written with the command number. As
soon as the MC_FCR register is written, the FRDY flag is automatically cleared. Once the current command is achieved,
then the FRDY flag is automatically set. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
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