SAM7X128_14 Datasheet, PDF (13/662 Pages) ATMEL Corporation – ARM-based Flash MCU

6. I/O Lines Considerations
6.1 JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up
resistor.
TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates
a permanent pull-down resistor of about 15 kΩ to GND.
To eliminate any risk of spuriously entering the JTAG boundary scan mode due to noise on JTAGSEL, it should be tied
externally to GND if boundary scan is not used, or pulled down with an external low-value resistor (such as 1 kΩ) .
6.2 Test Pin
The TST pin is used for manufacturing test or fast programming mode of the SAM7X512/256/128 when asserted high.
The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND.
To eliminate any risk of entering the test mode due to noise on the TST pin, it should be tied to GND if the FFPI is not
used, or pulled down with an external low-value resistor (such as 1 kΩ)
To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high and PA2 tied to low.
Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.
6.3 Reset Pin
The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset controller and can be
driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller.
There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length.
This allows connection of a simple push-button on the NRST pin as system user reset, and the use of the signal NRST to
reset all the components of the system.
The NRST pin integrates a permanent pull-up resistor to VDDIO.
6.4 ERASE Pin
The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down
resistor of about 15 kΩ to GND.
To eliminate any risk of erasing the Flash due to noise on the ERASE pin, it shoul be tied externally to GND, which
prevents erasing the Flash from the applicatiion, or pulled down with an external low-value resistor (such as 1 kΩ) .
This pin is debounced by the RC oscillator to improve the glitch tolerance. When the pin is tied to high during less than
100 ms, ERASE pin is not taken into account. The pin must be tied high during more than 220 ms to perform the re-
initialization of the Flash.
6.5 PIO Controller Lines
All the I/O lines, PA0 to PA30 and PB0 to PB30, are 5V-tolerant and all integrate a programmable pull-up resistor.
Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers.
5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to
5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled will
create a current path through the pull-up resistor from the I/O line to VDDIO. Care should be taken, in particular at reset,
as all the I/O lines default to input with pull-up resistor enabled at reset.
SAM7X Series [DATASHEET] 13
6120K–ATARM–11-Feb-14