SAM7X128_14 Datasheet, PDF (631/662 Pages) ATMEL Corporation – ARM-based Flash MCU

 Master Mode
 CPOL = 1 and NCPHA = 0
 Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock frequency
equals the system clock frequency) and the other transfers set with SCBR are not equal to 1
 Transmitting with the slowest chip select and then with the fastest one, then an additional pulse is generated on
output SPCK during the second transfer.
Problem Fix/Workaround
Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and the
others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
41.5.7.7 SPI: Software Reset must be Written Twice
If a software reset (SWRST in the SPI Control Register) is performed, the SPI may not work properly (the clock is
enabled before the chip select.)
Problem Fix/Workaround
The SPI Control Register field, SWRST (Software Reset) needs to be written twice to be correctly set.
41.5.8 Synchronous Serial Controller (SSC)
41.5.8.1 SSC: Periodic Transmission Limitations in Master Mode
If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
Problem Fix/Workaround
None.
41.5.8.2 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge (rising
or falling) of synchro has a Start Delay equal to zero.
Problem Fix/Workaround
None.
41.5.8.3 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as an input and TF is programmed as an output and requested to be set to low/high during data
emission, the Frame Synchro signal is generated one bit clock period after the data start and one data bit is lost. This
problem does not exist when generating a periodic synchro.
Problem Fix/Workaround
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
631