SAM7X128_14 Datasheet, PDF (304/662 Pages) ATMEL Corporation – ARM-based Flash MCU

30.6.3.5 Parity
The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR
field also enables the Multidrop mode, see “Multidrop Mode” on page 305. Even and odd parity bit generation and error
detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character
data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of
received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity
generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the
number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error
if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the
parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space
parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity
checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity
bit and the receiver does not report any parity error.
Table 30-6 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the
configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a
parity is even.
Table 30-6. Parity Bit Examples
Character
Hexa
A
0x41
A
0x41
A
0x41
A
0x41
A
0x41
Binary
0100 0001
0100 0001
0100 0001
0100 0001
0100 0001
Parity Bit
1
0
1
0
None
Parity Mode
Odd
Even
Mark
Space
None
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR).
The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 30-12 illustrates
the parity bit status setting and clearing.
Figure 30-12. Parity Error
Baud Rate
Clock
RXD
Write
US_CR
PARE
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Bad Stop
Parity Bit
Bit
RXRDY
RSTSTA = 1
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
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