SAM7X128_14 Datasheet, PDF (629/662 Pages) ATMEL Corporation – ARM-based Flash MCU

This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V.
I Leakage
Parameter
Typ
Max
I Leakage at 3,3V
2.5 µA 45 µA
Problem Fix/Workaround
It is recommended to use an external pull-up if needed.
41.5.4.2 PIO: Drive Low NRST, PA0-PA30 and PB0-PB26
When NRST or PA0 - PA30 or PB0 - PB26 are set as digital inputs with pull-up enabled, driving the I/O with an output
impedance higher than 500 ohms may not drive the I/O to a logical zero.
Problem Fix/Workaround
Output impedance must be lower than 500 ohms.
41.5.5 Pulse Width Modulation Controller (PWM)
41.5.5.1 PWM: Update when PWM_CCNTx = 0 or 1
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty Cycle Register is directly
modified when writing the Channel Update Register.
Problem Fix/Workaround
Check the Channel Counter Register before writing the update register.
41.5.5.2 PWM: Update when PWM_CPRDx = 0
When Channel Period Register equals 0, the period update is not operational.
Problem Fix/Workaround
Do not write 0 in the period register.
41.5.5.3 PWM: Counter Start Value
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1.
Problem Fix/Workaround
None.
41.5.5.4 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register
Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled by writing in the PWM_DIS
Register just after enabling it (before completion of a Clock Period of the clock selected for the channel), the PWM line is
internally disabled but the CHIDx status bit in the PWM_SR stays at 1.
Problem Fix/Workaround
Do not disable a channel before completion of one period of the selected clock.
41.5.6 Real Time Timer (RTT)
41.5.6.1 RTT: Possible Event Loss when Reading RTT_SR
If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the RTT_SR is read, the
corresponding bit might be cleared. This can lead to the loss of this event.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
629