SAM7X128_14 Datasheet, PDF (541/662 Pages) ATMEL Corporation – ARM-based Flash MCU

37.3.3 Pause Frame Support
The start of an 802.3 pause frame is as follows:
Table 37-3. Start of an 802.3 Pause Frame
Destination
Address
Source
Address
Type
(Mac Control Frame)
0x0180C2000001
6 bytes
0x8808
Pause
Opcode
0x0001
Pause Time
2 bytes
The network configuration register contains a receive pause enable bit (13). If a valid pause frame is received, the pause
time register is updated with the frame’s pause time, regardless of its current contents and regardless of the state of the
configuration register bit 13. An interrupt (12) is triggered when a pause frame is received, assuming it is enabled in the
interrupt mask register. If bit 13 is set in the network configuration register and the value of the pause time register is non-
zero, no new frame is transmitted until the pause time register has decremented to zero.
The loading of a new pause time, and hence the pausing of transmission, only occurs when the EMAC is configured for
full-duplex operation. If the EMAC is configured for half-duplex, there is no transmission pause, but the pause frame
received interrupt is still triggered.
A valid pause frame is defined as having a destination address that matches either the address stored in specific address
register 1 or matches 0x0180C2000001 and has the MAC control frame type ID of 0x8808 and the pause opcode of
0x0001. Pause frames that have FCS or other errors are treated as invalid and are discarded. Valid pause frames
received increment the Pause Frame Received statistic register.
The pause time register decrements every 512 bit times (i.e., 128 rx_clks in nibble mode) once transmission has
stopped. For test purposes, the register decrements every rx_clk cycle once transmission has stopped if bit 12 (retry
test) is set in the network configuration register. If the pause enable bit (13) is not set in the network configuration
register, then the decrementing occurs regardless of whether transmission has stopped or not.
An interrupt (13) is asserted whenever the pause time register decrements to zero (assuming it is enabled in the interrupt
mask register).
37.3.4 Receive Block
The receive block checks for valid preamble, FCS, alignment and length, presents received frames to the DMA block and
stores the frames destination address for use by the address checking block. If, during frame reception, the frame is
found to be too long or rx_er is asserted, a bad frame indication is sent to the DMA block. The DMA block then ceases
sending data to memory. At the end of frame reception, the receive block indicates to the DMA block whether the frame
is good or bad. The DMA block recovers the current receive buffer if the frame was bad. The receive block signals the
register block to increment the alignment error, the CRC (FCS) error, the short frame, long frame, jabber error, the
receive symbol error statistics and the length field mismatch statistics.
The enable bit for jumbo frames in the network configuration register allows the EMAC to receive jumbo frames of up to
10240 bytes in size. This operation does not form part of the IEEE802.3 specification and is disabled by default. When
jumbo frames are enabled, frames received with a frame size greater than 10240 bytes are discarded.
37.3.5 Address Checking Block
The address checking (or filter) block indicates to the DMA block which receive frames should be copied to memory.
Whether a frame is copied depends on what is enabled in the network configuration register, the state of the external
match pin, the contents of the specific address and hash registers and the frame’s destination address. In this
implementation of the EMAC, the frame’s source address is not checked. Provided that bit 18 of the Network
Configuration register is not set, a frame is not copied to memory if the EMAC is transmitting in half duplex mode at the
time a destination address is received. If bit 18 of the Network Configuration register is set, frames can be received while
transmitting in half-duplex mode.
Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet frame
make up the destination address. The first bit of the destination address, the LSB of the first byte of the frame, is the
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