SAM7X128_14 Datasheet, PDF (426/662 Pages) ATMEL Corporation – ARM-based Flash MCU

33.6.11 PWM Channel Period Register
Register Name:
PWM_CPRD[0. X-1]
Access Type:
Read-write
31
30
29
28
27
26
25
24
CPRD
23
22
21
20
19
18
17
16
CPRD
15
14
13
12
11
10
9
8
CPRD
7
6
5
4
3
2
1
0
CPRD
Only the first 16 bits (internal channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
(_---X_-----×_-----C_----P_----R_----D_-----)
MCK
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
(_---C_----R_----P_----D_------×_-----D_-----I_--V_----A_----)_-
MCK
or
(_---C_----R_----P_----D_------×_-----D_-----I_--V_----A_----B_----)_-
MCK
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
(_---2----×_-----X_-----×_-----C_-----P_----R_----D_----)_-
MCK
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
(_---2----×_-----C_-----P_----R_----D_------×_----D_-----I_--V_----A_----)_{- or} (_---2----×_-----C_-----P_----R_----D_-----×_-----D_-----I_--V_----B_----)_-
MCK
MCK
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
426