SAM7X128_14 Datasheet, PDF (199/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 26-6. Receiver Ready
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P
S D0 D1 D2 D3 D4 D5 D6 D7 P
RXRDY
Read DBGU_RHR
26.4.2.4 Receiver Overrun
If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY
bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the
software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1.
Figure 26-7.
Receiver Overrun
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S
D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY
OVRE
RSTSTA
26.4.2.5 Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field
PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in
DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is
written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is
written, the PARE bit remains at 1.
Figure 26-8.
Parity Error
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY
PARE
Wrong Parity Bit
RSTSTA
26.4.2.6 Receiver Framing Error
When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is
also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the
RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1.
Figure 26-9. Receiver Framing Error
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P ^stop
RXRDY
FRAME
Stop Bit
Detected at 0
RSTSTA
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
199