SAM7X128_14 Datasheet, PDF (64/662 Pages) ATMEL Corporation – ARM-based Flash MCU

13.2.6 Reset Controller Status Register
The Reset Controller status register (RSTC_SR) provides several status fields:
 RSTTYP field: This field gives the type of the last reset, as explained in previous sections.
 SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset
should be performed until the end of the current one. This bit is automatically cleared at the end of the current
software reset.
 NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising
edge.
 URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is
also detected on the Master Clock (MCK) rising edge (see Figure 13-9). If the User Reset is disabled (URSTEN =
0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an
interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt.
 BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). It
triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR
register resets the BODSTS bit and clears the interrupt.
Figure 13-9. Reset Controller Status and Interrupt
MCK
Peripheral Access
read
RSTC_SR
NRST
NRSTL
URSTS
rstc_irq
if (URSTEN = 0) and
(URSTIEN = 1)
2 cycle
resynchronization
2 cycle
resynchronization
SAM7X Series [DATASHEET] 64
6120K–ATARM–11-Feb-14