SAM7X128_14 Datasheet, PDF (497/662 Pages) ATMEL Corporation – ARM-based Flash MCU

 Timestamp interrupt: This interrupt is generated after the reception or the transmission of a start of frame or
an end of frame. The value of the internal counter is copied in the CAN_TIMESTP register.
All interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and the
timestamp interrupt. These interrupts are cleared by reading the CAN_SR register.
36.7.3 CAN Controller Message Handling
36.7.3.1 Receive Handling
Two modes are available to configure a mailbox to receive messages. In Receive Mode, the first message received is
stored in the mailbox data register. In Receive with Overwrite Mode, the last message received is stored in the mailbox.
36.7.3.2 Simple Receive Mailbox
A mailbox is in Receive Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and
Message Acceptance Mask must be set before the Receive Mode is enabled.
After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message
is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for
the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR
global register.
Message data are stored in the mailbox data register until the software application notifies that data processing has
ended. This is done by asking for a new transfer command, setting the MTCR flag in the CAN_MCRx register. This
automatically clears the MRDY signal.
The MMI flag in the CAN_MSRx register notifies the software that a message has been lost by the mailbox. This flag is
set when messages are received while MRDY is set in the CAN_MSRx register. This flag is cleared by reading the
CAN_MSRs register. A receive mailbox prevents from overwriting the first message by new ones while MRDY flag is set
in the CAN_MSRx register. See Figure 36-11.
Figure 36-11. Receive Mailbox
Message ID = CAN_MIDx
CAN BUS
MRDY
(CAN_MSRx)
MMI
(CAN_MSRx)
Message 1
Message 2 lost
Message 3
(CAN_MDLx
CAN_MDHx)
Message 1
MTCR
(CAN_MCRx)
Reading CAN_MDHx & CAN_MDLx
Reading CAN_MSRx
Writing CAN_MCRx
Message 3
Note:
In the case of ARM architecture, CAN_MSRx, CAN_MDLx, CAN_MDHx can be read using an optimized ldm assem-
bler instruction.
36.7.3.3 Receive with Overwrite Mailbox
A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx register has been configured.
Message ID and Message Acceptance masks must be set before Receive Mode is enabled.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
497