SAM7X128_14 Datasheet, PDF (410/662 Pages) ATMEL Corporation – ARM-based Flash MCU

33.5.2 PWM Channel
33.5.2.1 Block Diagram
Figure 33-3. Functional View of the Channel Block Diagram
inputs
from clock
generator
Channel
Clock
Selector
Internal
Counter
inputs from
APB bus
Comparator
PWMx
output waveform
Each of the 4 channels is composed of three blocks:
 A clock selector which selects one of the clocks provided by the clock generator described in Section 33.5.1 “PWM
Clock Generator” on page 409.
 An internal counter clocked by the output of the clock selector. This internal counter is incremented or
decremented according to the channel configuration and comparators events. The size of the internal counter is 16
bits.
 A comparator used to generate events according to the internal counter value. It also computes the PWMx output
waveform according to the configuration.
33.5.2.2 Waveform Properties
The different properties of output waveforms are:
 the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock
generator described in the previous section. This channel parameter is defined in the CPRE field of the
PWM_CMRx register. This field is reset at 0.
 the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
- If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be
calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
(_---X_-----×_-----C_----P_----R_----D_-----)
MCK
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
(_---C_----R_----P_----D_------×_-----D_-----I_--V_----A_----)_-
MCK
or
(_---C_----R_----P_----D_------×_-----D_-----I_--V_----A_----B_----)_-
MCK
If the waveform is center aligned then the output waveform period depends on the counter source clock and can
be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
(_---2----×_-----X_-----×_-----C_-----P_----R_----D_----)_-
MCK
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
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