SAM7X128_14 Datasheet, PDF (516/662 Pages) ATMEL Corporation – ARM-based Flash MCU

This flag is set depending on TEC counter value. A node is bus off when TEC counter is greater or equal to 256 (decimal).
This flag is automatically reset when above condition is not satisfied. Refer to Section 36.6.4.6 “Error Interrupt Handler” on page
492 for more information.
• SLEEP: CAN controller in Low power Mode
0 = CAN controller is not in low power mode.
1 = CAN controller is in low power mode.
This flag is automatically reset when Low power mode is disabled
• WAKEUP: CAN controller is not in Low power Mode
0 = CAN controller is in low power mode.
1 = CAN controller is not in low power mode.
When a WAKEUP event occurs, the CAN controller is synchronized with the bus activity. Messages can be transmitted or
received. The CAN controller clock must be available when a WAKEUP event occurs. This flag is automatically reset when the
CAN Controller enters Low Power mode.
• TOVF: Timer Overflow
0 = The timer has not rolled-over FFFFh to 0000h.
1 = The timer rolls-over FFFFh to 0000h.
This flag is automatically cleared by reading CAN_SR register.
• TSTP Timestamp
0 = No bus activity has been detected.
1 = A start of frame or an end of frame has been detected (according to the TEOF field in the CAN_MR register).
This flag is automatically cleared by reading the CAN_SR register.
• CERR: Mailbox CRC Error
0 = No CRC error occurred during a previous transfer.
1 = A CRC error occurred during a previous transfer.
A CRC error has been detected during last reception.
This flag is automatically cleared by reading CAN_SR register.
• SERR: Mailbox Stuffing Error
0 = No stuffing error occurred during a previous transfer.
1 = A stuffing error occurred during a previous transfer.
A form error results from the detection of more than five consecutive bit with the same polarity.
This flag is automatically cleared by reading CAN_SR register.
• AERR: Acknowledgment Error
0 = No acknowledgment error occurred during a previous transfer.
1 = An acknowledgment error occurred during a previous transfer.
An acknowledgment error is detected when no detection of the dominant bit in the acknowledge slot occurs.
This flag is automatically cleared by reading CAN_SR register.
• FERR: Form Error
0 = No form error occurred during a previous transfer
1 = A form error occurred during a previous transfer
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
516