SAM7X128_14 Datasheet, PDF (649/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Version
6120G
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Overview,
“Features” , TWI updated to include Atmel TWI compatibility with I²C Standard.
Section 7.4 ”Peripheral DMA Controller” updated with PDC priorities.
Section 10.8 ”Two-wire Interface”, updated.
Section 10.11 ”Timer Counter” The TC has Two output compare or one input capture per channel.
Section 10.15 ”Analog-to-Digital Converter” INL and DNL updated.
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4774
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4007
CAN, Figure 36-7,”Line Error Mode” Conditions to switch from Error Active mode to Error Passive mode and vice
versa have been inverted.
4089
Debug and Test,
Section 12.5.5 ”ID Code Register”, product part numbers and JTAG ID code values updated.
4382
DBGU,
Section 26.5.10 ”Debug Unit Chip ID Register”, SRAM bit description added for AT91SAM7L in the bit field.
“SRAMSIZ: Internal SRAM Size” on page 216
Corrected bin values for 0x60 and 0xF0 and Architecture Identifier bit description for CAP7, AT91SAM7AQxx
Series and CAP11 in the bit description, “ARCH: Architecture Identifier” on page 217
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3369,
3807
EMAC,
Section 37.5.3 “Network Status Register” on page 553, Corrected status for IDLE bit.
Section 37.3 “Functional Description” on page 536, Added information on clocks in first paragraph.
3326
3328
FFPI,
Table 20-6, Table 20-9, Table 20-18 updated
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Global update to terms listed below:
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Fuse → GPNVM
SFB → SGPB
CFB → CGPB
GFB → GGPB
Section 20.2.5.6 on page 119 & Section 20.3.4.6 on page 126, security bit restraint on access to FFPI explained. 4744
PIO,
Section 27.4.5 “Synchronous Data Output” on page 223, PIO_OWSR typo corrected.
Section 27.6 “Parallel Input/Output Controller (PIO) User Interface” on page 227, 10, footnotes updated on
PIO_PSR, PIO_ODSR, PIO_PDSR in Register Mapping table.
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PMC,
Section 25.3 ”Processor Clock Controller” ....the processor clock can be disabled by writing.... PMC_SDR.
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Figure 24-2,”Typical Crystal Connection” updated, removed C_L1 and C_L2 labels.
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PWM,
Section 33.6 “Pulse Width Modulation Controller (PWM) User Interface” on page 415, the Offset column in Table
33-2, Register Mapping ; the PWM channel-dependent registers listed as indexed registers.
See Section 33.6.9 ”PWM Channel Mode Register”, Section 33.6.10 ”PWM Channel Duty Cycle Register”,
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Section 33.6.11 ”PWM Channel Period Register”, Section 33.6.12 ”PWM Channel Counter Register”, and
Section 33.6.13 ”PWM Channel Update Register”;
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
649