SAM7X128_14 Datasheet, PDF (300/662 Pages) ATMEL Corporation – ARM-based Flash MCU

The Receiver and the Transmitter can be enabled together or independently.
At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the
corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the
status flag and reset internal state machines but the user interface configuration registers hold the value configured prior
to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately
stopped.
The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in
US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current
character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of
transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a
timeguard is programmed, it is handled normally.
30.6.3 Synchronous and Asynchronous Modes
30.6.3.1 Transmitter Operations
The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1).
One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin
at each falling edge of the programmed serial clock.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are
selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in
US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which
data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number
of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only.
Figure 30-6. Character Transmit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock
TXD
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop
Bit
Bit Bit
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in
the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and
TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character
processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and
US_THR becomes empty, thus TXRDY raises.
Both TXRDY and TXEMPTY bits are low since the transmitter is disabled. Writing a character in US_THR while TXRDY
is active has no effect and the written character is lost.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
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