SAM7X128_14 Datasheet, PDF (377/662 Pages) ATMEL Corporation – ARM-based Flash MCU

32.5 Functional Description
32.5.1 TC Description
The three channels of the Timer Counter are independent and identical in operation. The registers for channel
programming are listed in Table 32-4 on page 389.
32.5.2 16-bit Counter
Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the
selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the
COVFS bit in TC_SR (Status Register) is set.
The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter
can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock.
32.5.3 Clock Selection
At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or
TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR
(Block Mode). See Figure 32-2 on page 378.
Each channel can independently select an internal or external clock source for its counter:
 Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5
 External clock signals: XC0, XC1 or XC2
This selection is made by the TCCLKS bits in the TC Channel Mode Register.
The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the
clock.
The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode
Register defines this signal (none, XC0, XC1, XC2). See Figure 32-3 on page 378
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock
period. The external clock frequency must be at least 2.5 times lower than the master clock
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
377