SAM7X128_14 Datasheet, PDF (552/662 Pages) ATMEL Corporation – ARM-based Flash MCU

• CLK: MDC clock divider
Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For con-
formance with 802.3, MDC must not exceed 2.5MHz (MDC is only active during MDIO read and write operations).
CLK
00
01
10
11
MDC
MCK divided by 8 (MCK up to 20 MHz)
MCK divided by 16 (MCK up to 40 MHz)
MCK divided by 32 (MCK up to 80 MHz)
MCK divided by 64 (MCK up to 160 MHz)
• RTY: Retry test
Must be set to zero for normal operation. If set to one, the back off between collisions is always one slot time. Setting this bit to
one helps testing the too many retries condition. Also used in the pause frame tests to reduce the pause counters decrement time
from 512 bit times, to every rx_clk cycle.
• PAE: Pause Enable
When set, transmission pauses when a valid pause frame is received.
• RBOF: Receive Buffer Offset
Indicates the number of bytes by which the received data is offset from the start of the first receive buffer.
RBOF
00
01
10
11
Offset
No offset from start of receive buffer
One-byte offset from start of receive buffer
Two-byte offset from start of receive buffer
Three-byte offset from start of receive buffer
• RLCE: Receive Length field Checking Enable
When set, frames with measured lengths shorter than their length fields are discarded. Frames containing a type ID in bytes 13
and 14 — length/type ID = 0600 — are not be counted as length errors.
• DRFCS: Discard Receive FCS
When set, the FCS field of received frames are not be copied to memory.
• EFRHD:
Enable Frames to be received in half-duplex mode while transmitting.
• IRXFCS: Ignore RX FCS
When set, frames with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit
must be set to 0.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
552