SAM7X128_14 Datasheet, PDF (135/662 Pages) ATMEL Corporation – ARM-based Flash MCU

The size of the buffer (number of transfers) is configured in an internal 16-bit transfer counter register, and it is possible,
at any moment, to read the number of transfers left for each channel.
The memory base address is configured in a 32-bit memory pointer by defining the location of the first address to access
in the memory. It is possible, at any moment, to read the location in memory of the next transfer and the number of
remaining transfers. The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each
channel. The status for each channel is located in the peripheral status register. Transfers can be enabled and/or
disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in PDC Transfer Control Register. These control bits enable
reading the pointer and counter registers safely without any risk of their changing between both reads.
The PDC sends status flags to the peripheral visible in its status-register (ENDRX, ENDTX, RXBUFF, and TXBUFE).
ENDRX flag is set when the PERIPH_RCR register reaches zero.
RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero.
ENDTX flag is set when the PERIPH_TCR register reaches zero.
TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero.
These status flags are described in the peripheral status register.
22.3.2 Memory Pointers
Each peripheral is connected to the PDC by a receiver data channel and a transmitter data channel. Each channel has
an internal 32-bit memory pointer. Each memory pointer points to a location anywhere in the memory space (on-chip
memory or external bus interface memory).
Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented by 1, 2 or 4, respectively
for peripheral transfers.
If a memory pointer is reprogrammed while the PDC is in operation, the transfer address is changed, and the PDC
performs transfers using the new address.
22.3.3 Transfer Counters
There is one internal 16-bit transfer counter for each channel used to count the size of the block already transferred by its
associated channel. These counters are decremented after each data transfer. When the counter reaches zero, the
transfer is complete and the PDC stops transferring data.
If the Next Counter Register is equal to zero, the PDC disables the trigger while activating the related peripheral end flag.
If the counter is reprogrammed while the PDC is operating, the number of transfers is updated and the PDC counts
transfers from the new value.
Programming the Next Counter/Pointer registers chains the buffers. The counters are decremented after each data
transfer as stated above, but when the transfer counter reaches zero, the values of the Next Counter/Pointer are loaded
into the Counter/Pointer registers in order to re-enable the triggers.
For each channel, two status bits indicate the end of the current buffer (ENDRX, ENTX) and the end of both current and
next buffer (RXBUFF, TXBUFE). These bits are directly mapped to the peripheral status register and can trigger an
interrupt request to the AIC.
The peripheral end flag is automatically cleared when one of the counter-registers (Counter or Next Counter Register) is
written.
Note: When the Next Counter Register is loaded into the Counter Register, it is set to zero.
22.3.4 Data Transfers
The peripheral triggers PDC transfers using transmit (TXRDY) and receive (RXRDY) signals.
When the peripheral receives an external character, it sends a Receive Ready signal to the PDC which then requests
access to the system bus. When access is granted, the PDC starts a read of the peripheral Receive Holding Register
(RHR) and then triggers a write in the memory.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
135