SAM7X128_14 Datasheet, PDF (93/662 Pages) ATMEL Corporation – ARM-based Flash MCU

 the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP)
 whether the access is due to accessing an undefined address (bit UNDADD) or a misaligned address (bit
MISADD)
 the source of the access leading to the last abort (bits MST_EMAC, MST_PDC and MST_ARM)
 whether or not an abort occurred for each master since the last read of the register (bits SVMST_EMAC,
SVMST_PDC and SVMST_ARM) unless this information is loaded in MST bits
In the case of a Data Abort from the processor, the address of the data access is stored. This is useful, as searching for
which address generated the abort would require disassembling the instructions and full knowledge of the processor
context.
In the case of a Prefetch Abort, the address may have changed, as the prefetch abort is pipelined in the ARM processor.
The ARM processor takes the prefetch abort into account only if the read instruction is executed and it is probable that
several aborts have occurred during this time. Thus, in this case, it is preferable to use the content of the Abort Link
register of the ARM processor.
18.3.5 Embedded Flash Controller
The Embedded Flash Controller is added to the Memory Controller and ensures the interface of the flash block with the
32-bit internal bus. It allows an increase of performance in Thumb Mode for Code Fetch with its system of 32-bit buffers.
It also manages with the programming, erasing, locking and unlocking sequences thanks to a full set of commands.
18.3.6 Misalignment Detector
The Memory Controller features a Misalignment Detector that checks the consistency of the accesses.
For each access, regardless of the master, the size of the access and the bits 0 and 1 of the address bus are checked. If
the type of access is a word (32-bit) and the bits 0 and 1 are not 0, or if the type of the access is a half-word (16-bit) and
the bit 0 is not 0, an abort is returned to the master and the access is cancelled. Note that the accesses of the ARM
processor when it is fetching instructions are not checked.
The misalignments are generally due to software bugs leading to wrong pointer handling. These bugs are particularly
difficult to detect in the debug phase.
As the requested address is saved in the Abort Status Register and the address of the instruction generating the
misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bugs is
simplified.
SAM7X Series [DATASHEET] 93
6120K–ATARM–11-Feb-14