SAM7X128_14 Datasheet, PDF (430/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit
values to APB registers.
The UDP peripheral requires two clocks: one peripheral clock used by the MCK domain and a 48 MHz clock used by the
12 MHz domain.
A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).
The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode. The host is then
notified that the device asks for a resume. This optional feature must be also negotiated with the host during the
enumeration.
34.3
Product Dependencies
For further details on the USB Device hardware implementation, see the specific Product Properties document.
The USB physical transceiver is integrated into the product. The bidirectional differential signals DP and DM are
available from the product boundary.
Two I/O lines may be used by the application:
 One to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that
the host has been powered off. In this case, the board pullup on DP must be disabled in order to prevent feeding
current to the host.
 One to control the board pullup on DP. Thus, when the device is ready to communicate with the host, it activates its
DP pullup through this control line.
34.3.1 I/O Lines
DP and DM are not controlled by any PIO controllers. The embedded USB physical transceiver is controlled by the USB
device peripheral.
To reserve an I/O line to check VBUS, the programmer must first program the PIO controller to assign this I/O in input
PIO mode.
To reserve an I/O line to control the board pullup, the programmer must first program the PIO controller to assign this I/O
in output PIO mode.
34.3.2 Power Management
The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL with an accuracy of ±
0.25%.
Thus, the USB device receives two clocks from the Power Management Controller (PMC): the master clock, MCK, used
to drive the peripheral user interface, and the UDPCK, used to interface with the bus USB signals (recovered 12 MHz
domain).
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any
read/write operations to the UDP registers including the UDP_TXCV register.
34.3.3 Interrupt
The USB device interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling the USB device interrupt requires programming the AIC before configuring the UDP.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
430