SAM7X128_14 Datasheet, PDF (92/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 18-3.
Internal Memory Mapping
0x0000 0000
0x000F FFFF
0x0010 0000
256M Bytes
0x001F FFFF
0x0020 0000
0x002F FFFF
0x0030 0000
0x003F FFFF
0x0040 0000
Internal Memory Area 0
Internal Memory Area 1
Internal Flash
Internal Memory Area 2
Internal SRAM
Internal Memory Area 3
Internal ROM
Undefined Areas
(Abort)
0x0FFF FFFF
1 M Bytes
1 M Bytes
1 M Bytes
1 M Bytes
252 M Bytes
18.3.2.2 Internal Memory Area 0
The first 32 bytes of Internal Memory Area 0 contain the ARM processor exception vectors, in particular, the Reset
Vector at address 0x0.
Before execution of the remap command, the on-chip Flash is mapped into Internal Memory Area 0, so that the
ARM7TDMI reaches an executable instruction contained in Flash. After the remap command, the internal SRAM at
address 0x0020 0000 is mapped into Internal Memory Area 0. The memory mapped into Internal Memory Area 0 is
accessible in both its original location and at address 0x0.
18.3.3 Remap Command
After execution, the Remap Command causes the Internal SRAM to be accessed through the Internal Memory Area 0.
As the ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, and Fast Interrupt) are
mapped from address 0x0 to address 0x20, the Remap Command allows the user to redefine dynamically these vectors
under software control.
The Remap Command is accessible through the Memory Controller User Interface by writing the MC_RCR (Remap
Control Register) RCB field to one.
The Remap Command can be cancelled by writing the MC_RCR RCB field to one, which acts as a toggling command.
This allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the same
configuration as after a reset.
18.3.4 Abort Status
There are two reasons for an abort to occur:
 access to an undefined address
 an access to a misaligned address.
When an abort occurs, a signal is sent back to all the masters, regardless of which one has generated the access.
However, only the ARM7TDMI can take an abort signal into account, and only under the condition that it was generating
an access. The Peripheral DMA Controller and the EMAC do not handle the abort input signal. Note that the connections
are not represented in Figure 18-1.
To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates an Abort Status register
set.
The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved in MC_ASR and include:
 the size of the request (field ABTSZ)
SAM7X Series [DATASHEET] 92
6120K–ATARM–11-Feb-14