SAM7X128_14 Datasheet, PDF (198/662 Pages) ATMEL Corporation – ARM-based Flash MCU

26.4.2 Receiver
26.4.2.1 Receiver Reset, Enable and Disable
After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be
enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for
a start bit.
The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a
start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it
waits for the stop bit before actually stopping its operation.
The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the
receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when
data is being processed, this data is lost.
26.4.2.2 Start Detection and Data Sampling
The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver
detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space)
on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times
the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is
7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit.
When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is
assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit
period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the
start bit was detected.
Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
Figure 26-4. Start Bit Detection
Sampling Clock
DRXD
True Start
D0
Detection
Baud Rate
Clock
Figure 26-5. Character Reception
Example: 8-bit, parity enabled 1 stop
0.5 bit 1 bit
period period
DRXD
Sampling
D0 D1 D2 D3 D4 D5 D6 D7
Stop Bit
True Start Detection
Parity Bit
26.4.2.3 Receiver Ready
When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR
(Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read.
SAM7X Series [DATASHEET]
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