SAM7X128_14 Datasheet, PDF (360/662 Pages) ATMEL Corporation – ARM-based Flash MCU

31.8.6 SSC Transmit Frame Mode Register
Name:
SSC_TFMR
Access Type:
Read-write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
FSEDGE
23
22
21
20
19
18
17
16
FSDEN
FSOS
FSLEN
15
14
13
12
11
10
9
8
–
–
–
–
DATNB
7
6
5
4
3
2
1
0
MSBF
–
DATDEF
DATLEN
• DATLEN: Data Length
0: Forbidden value (1-bit data length not supported).
Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2
assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15 (included),
half-words are transferred, and for any other value, 32-bit words are transferred.
• DATDEF: Data Default Value
This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO
Controller, the pin is enabled only if the SCC TD output is 1.
• MSBF: Most Significant Bit First
0: The lowest significant bit of the data register is shifted out first in the bit stream.
1: The most significant bit of the data register is shifted out first in the bit stream.
• DATNB: Data Number per frame
This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1).
• FSLEN: Transmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data
Register if FSDEN is 1.
Pulse length is equal to (FSLEN + 1) Transmit Clock periods, i.e., the pulse length can range from 1 to 16 Transmit Clock periods.
If FSLEN is 0, the Transmit Frame Sync signal is generated during one Transmit Clock period.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
360