SAM7X128_14 Datasheet, PDF (223/662 Pages) ATMEL Corporation – ARM-based Flash MCU

27.4.5 Synchronous Data Output
Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and
PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO
outputs by single write access to PIO_ODSR (Output Data Status Register). Only bits unmasked by PIO_OWSR (Output
Write Status Register) are written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write
Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.
27.4.6 Multi Drive Control (Open Drain)
Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several
drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling
of the internal one) is generally required to guarantee a high level on the line.
The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable
Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a
peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external
drivers.
After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
27.4.7 Output Line Timings
Figure 27-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing
PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 27-4 also shows when the
feedback in PIO_PDSR is available.
Figure 27-4. Output Line Timings
MCK
Write PIO_SODR
Write PIO_ODSR at 1
Write PIO_CODR
Write PIO_ODSR at 0
PIO_ODSR
PIO_PDSR
APB Access
2 cycles
APB Access
2 cycles
27.4.8 Inputs
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of
the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a
peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels
present on the I/O line at the time the clock was disabled.
27.4.9 Input Glitch Filtering
Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch
with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1
SAM7X Series [DATASHEET]
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