SAM7X128_14 Datasheet, PDF (151/662 Pages) ATMEL Corporation – ARM-based Flash MCU

 Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level
is the priority level of the current interrupt.
 De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to
de-assert nIRQ.
 Automatically clears the interrupt, if it has been programmed to be edge-triggered.
 Pushes the current level and the current interrupt number on to the stack.
 Returns the value written in the AIC_SVR corresponding to the current interrupt.
4. The previous step has the effect of branching to the corresponding interrupt service routine. This should start by
saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved
if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction SUB
PC, LR, #4 may be used.
5. Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing re-assertion of the nIRQ to be
taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt
occurs.
6. The interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the
end. During this phase, an interrupt of higher priority than the current level will restart the sequence from step 1.
Note: If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase.
7. The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed
in an orderly manner.
8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the cur-
rent interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current
level if one exists on the stack. If another interrupt is pending, with lower or equal priority than the old current level
but with higher priority than the new current level, the nIRQ line is re-asserted, but the interrupt sequence does not
immediately start because the “I” bit is set in the core. SPSR_irq is restored. Finally, the saved value of the link reg-
ister is restored directly into the PC. This has the effect of returning from the interrupt to whatever was being
executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending
on the state saved in SPSR_irq.
Note:
The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an inter-
rupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is
completed (interrupt is masked).
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
151