SAM7X128_14 Datasheet, PDF (47/662 Pages) ATMEL Corporation – ARM-based Flash MCU

12.5.2 EmbeddedICE (Embedded In-circuit Emulator)
The ARM7TDMI EmbeddedICE is supported via the ICE/JTAG port. The internal state of the ARM7TDMI is examined
through an ICE/JTAG port.
The ARM7TDMI processor contains hardware extensions for advanced debugging features:
 In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the
ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system.
 In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor program
running on the ARM7TDMI processor.
There are three scan chains inside the ARM7TDMI processor that support testing, debugging, and programming of the
EmbeddedICE. The scan chains are controlled by the ICE/JTAG port.
EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG
operations. A chip reset must be performed after JTAGSEL is changed.
For further details on the EmbeddedICE, see the ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B).
12.5.3 Debug Unit
The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes
and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the
association with two peripheral data controller channels permits packet handling of these tasks with processor time
reduced to a minimum.
The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and
that trace the activity of the Debug Communication Channel. The Debug Unit allows blockage of access to the system
through the ICE interface.
A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal
configuration.
The SAM7X512 Debug Unit Chip ID value is 0x275C 0A40 on 32-bit width.
The SAM7X256 Debug Unit Chip ID value is 0x275B 0940 on 32-bit width.
The SAM7X128 Debug Unit Chip ID value is 0x275A 0740 on 32-bit width.
For further details on the Debug Unit, see the Debug Unit section.
12.5.4 IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions
are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the
processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is
changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
12.5.4.1 JTAG Boundary-scan Register
The Boundary-scan Register (BSR) contains 187 bits that correspond to active pins and associated control signals.
SAM7X Series [DATASHEET] 47
6120K–ATARM–11-Feb-14