SAM7X128_14 Datasheet, PDF (650/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Version
6120G
(Continued) ^Comments
Change
Request
Ref.
SPI,
Section 28.6.4 “SPI Slave Mode” on page 254, corrected information on OVRES (SPI_SR) and data read in
SPI_RDR.
3943
SSC,
Section 31.6.5.1 ”Frame Sync Data”, defined max Frame Sync Data length.
Section 31.6.6.1 ”Compare Functions”, updated with max FSLEN length.
2293
TC,
Figure 32-2,”Clock Chaining Selection”, added to Section 32.5 ”Functional Description”.
Section 32.6 ”Timer Counter (TC) User Interface” Register mapping tables consolidated in Table 32-4 on page
389 and register offsets indexed.
3342
4583
Section 32.6.3 on page 392 to Section 32.6.13 on page 406, register names updated with indexed offset.
Section 32.6.4 ”TC Channel Mode Register: Capture Mode” bit field 15 and WAVE bit field description updated.
TWI,
“Two-wire Interface (TWI)” , section has been updated.
Important changes to this datasheet include a clarification of Atmel TWI compatibility with I²C Standard.
4247
UDP,
Table 34-2, “USB Communication Flow”, Supported Endpoint column updated.
In the USB_CSR register, the control endpoints are not effected by the bit field, “EPEDS: Endpoint Enable
Disable” on page 475
Updated: write 1 =.... in “RX_DATA_BK0: Receive Data Bank 0” bit field of USB_CSR register.
Updated: write 0 = ....in “TXPKTRDY: Transmit Packet Ready” bit field of USB_CSR register.
3476
4063
4099
Section 34.6.10 “UDP Endpoint Control and Status Register” on page 457, update to code and added
4462
instructions regarding USB clock and system clock cycle, and updated “note” appearing under the code.
4487
“wait 3 USB clock cycles and 3 system clock cycles before accessing DPR from RX_DATAx and TXPKTRDY bit
fields, ditto for RX_DATAx and TXPKTRDY bit field descriptions.”
4508
Section 34.2 ”Block Diagram”, in the text below the block diagram, MCK specified as clock used by Master Clock
domain, UDPCK specified as 48 MHz clock used by 12 MHz domain, in peripheral clock requirements.
Section 34.6 ”USB Device Port (UDP) User Interface”, The register mapping table has been updated
Section 34.6.6 ”UDP Interrupt Mask Register” Bit 12 of has been defined as BIT12 and cannot be masked.
4802
USART,
“CLKO: Clock Output Select” on page 323, bit field in US_MR register, typo fixed in bit field description.
3306
“USCLKS: Clock Selection” on page 321, bit field in US_MR register, DIV= 8 in Selected Clock column.
3763
Section 30.5.1 ”I/O Lines”, 2nd and 3rd paragraphsupdated.
3851/4285
“TXEMPTY: Transmitter Empty” on page 328, no characters when at 1 updated.
3895
Section 30.6.2 ”Receiver and Transmitter Control”, In the fourth paragraph, Software reset effects (RSTRX and ⁴³⁶⁷
RSTTX in US_CR register) updated by replacing 2nd sentence.
Section 30.6.5 ”IrDA Mode”, updated with instruction to receive IrDA signals.
Section 30.2 ”Block Diagram”, signal directions from pads to PIO updated in the block diagram.
4912
4905
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
650