SAM7X128_14 Datasheet, PDF (540/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Table 37-2. Transmit Buffer Descriptor Entry (Continued)
Bit
Function
Used. Needs to be zero for the EMAC to read data from the transmit buffer. The EMAC sets this to one for the first buffer
of a frame once it has been successfully transmitted.
31
Software has to clear this bit before the buffer can be used again.
Note: This bit is only set for the first buffer in a frame unlike receive where all buffers have the Used bit set once
used.
30
Wrap. Marks last descriptor in transmit buffer descriptor list.
29
Retry limit exceeded, transmit error detected
28
Transmit underrun, occurs either when hresp is not OK (bus error) or the transmit data could not be fetched in time or
when buffers are exhausted in mid frame.
27
Buffers exhausted in mid frame
26:17 Reserved
16
No CRC. When set, no CRC is appended to the current frame. This bit only needs to be set for the last buffer of a frame.
15
Last buffer. When set, this bit indicates the last buffer in the current frame has been reached.
14:11 Reserved
10:0 Length of buffer
37.3.2 Transmit Block
This block transmits frames in accordance with the Ethernet IEEE 802.3 CSMA/CD protocol. Frame assembly starts by
adding preamble and the start frame delimiter. Data is taken from the transmit FIFO a word at a time. Data is transmitted
least significant nibble first. If necessary, padding is added to increase the frame length to 60 bytes. CRC is calculated as
a 32-bit polynomial. This is inverted and appended to the end of the frame, taking the frame length to a minimum of 64
bytes. If the No CRC bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor CRC
are appended.
In full-duplex mode, frames are transmitted immediately. Back-to-back frames are transmitted at least 96 bit times apart
to guarantee the interframe gap.
In half-duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to de-assert and then starts
transmission after the interframe gap of 96 bit times. If the collision signal is asserted during transmission, the transmitter
transmits a jam sequence of 32 bits taken from the data register and then retry transmission after the back off time has
elapsed.
The back-off time is based on an XOR of the 10 least significant bits of the data coming from the transmit FIFO and a 10-
bit pseudo random number generator. The number of bits used depends on the number of collisions seen. After the first
collision, 1 bit is used, after the second 2, and so on up to 10. Above 10, all 10 bits are used. An error is indicated and no
further attempts are made if 16 attempts cause collisions.
If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as jam insertion and the
tx_er signal is asserted. For a properly configured system, this should never happen.
If the back pressure bit is set in the network control register in half duplex mode, the transmit block transmits 64 bits of
data, which can consist of 16 nibbles of 1011 or in bit-rate mode 64 1s, whenever it sees an incoming frame to force a
collision. This provides a way of implementing flow control in half-duplex mode.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
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