SAM7X128_14 Datasheet, PDF (355/662 Pages) ATMEL Corporation – ARM-based Flash MCU

• CKG: Receive Clock Gating Selection
CKG
Receive Clock Gating
0x0
None, continuous clock
0x1
Receive Clock enabled only if RF Low
0x2
Receive Clock enabled only if RF High
0x3
Reserved
• START: Receive Start Selection
START
Receive Start
0x0
Continuous, as soon as the receiver is enabled, and immediately after the end of
transfer of the previous data.
0x1
Transmit start
0x2
Detection of a low level on RF signal
0x3
Detection of a high level on RF signal
0x4
Detection of a falling edge on RF signal
0x5
Detection of a rising edge on RF signal
0x6
Detection of any level change on RF signal
0x7
Detection of any edge on RF signal
0x8
Compare 0
0x9-0xF Reserved
• STOP: Receive Stop Selection
0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a
new compare 0.
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
• STTDLY: Receive Start Delay
If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the
Receiver is programmed to start synchronously with the Transmitter, the delay is also applied.
Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync
Data) reception.
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no
PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
355