SAM7X128_14 Datasheet, PDF (437/662 Pages) ATMEL Corporation – ARM-based Flash MCU

1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the end-
point’s UDP_ CSRx register.
2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values
in the endpoint’s UDP_ FDRx register.
3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPK-
TRDY in the endpoint’s UDP_ CSRx register.
4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the
FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_ FDRx register.
5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the end-
point’s UDP_ CSRx register is set. An interrupt is pending while TXCOMP is being set.
6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared
the second Bank to be sent rising TXPKTRDY in the endpoint’s UDP_ CSRx register.
7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent.
Figure 34-8. Data IN Transfer for Ping-pong Endpoint
Microcontroller
Microcontroller Load Data IN Bank 1
Load Data IN Bank 0 _{USB Device Send Bank 0}
Microcontroller Load Data IN Bank 0
USB Device Send Bank 1
USB Bus
Packets
Data IN
PID
Data IN
ACK
PID
Data IN
PID
Data IN
ACK
PID
TXPKTRDY Flag
(UDP_MCSRx)
TXCOMP Flag
(UDP_CSRx)
Cleared by USB Device,
Set by Firmware,
Data Payload Fully Transmitted
Data Payload Written in FIFO Bank 0
Set by USB
Device
Set by Firmware,
Data Payload Written in FIFO Bank 1
Interrupt Pending
Set by USB Device
Interrupt Cleared by Firmware
FIFO (DPR) _{Written by}
Bank 0
Microcontroller
Read by USB Device
Written by
Microcontroller
FIFO (DPR)
Bank 1
Written by
Microcontroller
Read by USB Device
Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for
TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set is too long,
some Data IN packets may be NACKed, reducing the bandwidth.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
34.5.2.3 Data OUT Transaction
Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data
from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-
pong attributes.
Data OUT Transaction Without Ping-pong Attributes
To perform a Data OUT transaction, using a non ping-pong endpoint:
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
437