SAM7X128_14 Datasheet, PDF (283/662 Pages) ATMEL Corporation – ARM-based Flash MCU

29.6.1 TWI Control Register
Register Name:
Access Type:
TWI_CR
Write-only
31
30
29
–
–
–
23
22
21
–
–
–
15
14
13
–
–
–
7
6
5
SWRST
–
–
28
27
26
25
24
–
–
–
–
–
20
19
18
17
16
–
–
–
–
–
12
11
10
9
8
–
–
–
–
–
4
3
2
1
0
–
MSDIS
MSEN
STOP
START
• START: Send a START Condition
0 = No effect.
1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write
operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR).
• STOP: Send a STOP Condition
0 = No effect.
1 = STOP Condition is sent just after completing the current byte transmission in master read mode.
– In single data byte master read, the START and STOP must both be set.
– In multiple data bytes master read, the STOP must be set after the last data received but one.
– In master read mode, if a NACK bit is received, the STOP is automatically performed.
– In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically
sent.
• MSEN: TWI Master Transfer Enabled
0 = No effect.
1 = If MSDIS = 0, the master data transfer is enabled.
• MSDIS: TWI Master Transfer Disabled
0 = No effect.
1 = The master data transfer is disabled, all pending data is transmitted. The shifter and holding characters (if they contain data)
are transmitted in case of write operation. In read operation, the character being transferred must be completely received before
disabling.
• SWRST: Software Reset
0 = No effect.
1 = Equivalent to a system reset.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
283