SAM7X128_14 Datasheet, PDF (341/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO
field) might lead to unpredictable results.
Figure 31-6. Transmitter Clock Management
TK
SSC_TCMR.CKS
SSC_TCMR.CKO
Receiver Clock
Divider Clock
TK
0
Transmitter Clock
1
SSC_TCMR.CKI
31.6.1.3 Receiver Clock Management
The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O
pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can
be inverted independently by the CKI bits in SSC_RCMR.
The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is
configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs.
Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO
field) can lead to unpredictable results.
Figure 31-7. Receiver Clock Management
RK
SSC_RCMR.CKS
SSC_RCMR.CKO
Transmitter Clock
Divider Clock
RK
0
Receiver Clock
1
SSC_RCMR.CKI
31.6.1.4 Serial Clock Ratio Considerations
The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK
pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on
the RK pin is:
 Master Clock divided by 2 if Receiver Frame Synchro is input
 Master Clock divided by 3 if Receiver Frame Synchro is output
In addition, the maximum clock speed allowed on the TK pin is:
 Master Clock divided by 6 if Transmit Frame Synchro is input
 Master Clock divided by 2 if Transmit Frame Synchro is output
31.6.2 Transmitter Operations
A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission.
The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 343.
The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on
page 345.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
341