SAM7X128_14 Datasheet, PDF (16/662 Pages) ATMEL Corporation – ARM-based Flash MCU

 Embedded Flash Controller
 Embedded Flash interface, up to three programmable wait states
 Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states
 Key-protected program, erase and lock/unlock sequencer
 Single command for erasing, programming and locking operations
 Interrupt generation in case of forbidden operation
7.4 Peripheral DMA Controller
 Handles data transfer between peripherals and memories
 Thirteen channels
 Two for each USART
 Two for the Debug Unit
 Two for the Serial Synchronous Controller
 Two for each Serial Peripheral Interface
 One for the Analog-to-digital Converter
 Low bus arbitration overhead
 One Master Clock cycle needed for a transfer from memory to peripheral
 Two Master Clock cycles needed for a transfer from peripheral to memory
 Next Pointer management for reducing interrupt latency requirements
 Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest):
Receive
Receive
Receive
Receive
Receive
Receive
Receive
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
DBGU
USART0
USART1
SSC
ADC
SPI0
SPI1
DBGU
USART0
USART
SSC
SPI0
SPI1
SAM7X Series [DATASHEET] 16
6120K–ATARM–11-Feb-14