LM3S8G62 Datasheet, PDF (980/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

Signal Tables
OBSOLETE: TI has discontinued production of this device.
Table 22-2. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
51
HIB
O
OD
An output that indicates the processor is in Hibernate mode.
XOSC0
52
I
Analog Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a 4.194304-MHz crystal or
a 32.768-kHz oscillator for the Hibernation module RTC. See the
CLKSEL bit in the HIBCTL register.
53
XOSC1
O
Analog Hibernation module oscillator crystal output. Leave unconnected
when using a single-ended clock source.
54
GND
-
Power Ground reference for logic and I/O pins.
VBAT
55
-
Power Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
56
VDD
-
Power Positive supply for I/O and some logic.
57
GND
-
Power Ground reference for logic and I/O pins.
58
MDIO
I/O
OD
MDIO of the Ethernet PHY.
PF3
I/O
TTL
GPIO port F bit 3.
LED0
O
TTL
Ethernet LED 0.
59
PWM3
O
TTL
PWM 3. This signal is controlled by PWM Generator 1.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
PF2
I/O
TTL
GPIO port F bit 2.
LED1
O
TTL
Ethernet LED 1.
60
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
PF1
I/O
TTL
GPIO port F bit 1.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
61
IDX1
I
TTL
QEI module 1 index.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
VDDC
62
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 24-6 on page 1036 .
63
GND
-
Power Ground reference for logic and I/O pins.
64
RST
I
TTL
System reset input.
65
CMOD0
I
TTL
CPU Mode bit 0. Input must be set to logic 0 (grounded); other
encodings reserved.
PB0
I/O
TTL
GPIO port B bit 0. This pin is not 5-V tolerant.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
66
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
980
July 24, 2012
Texas Instruments-Production Data