LM3S8G62 Datasheet, PDF (643/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S8G62 Microcontroller
Bit/Field
14
13:12
11
10
9
8
7
Name
RTSEN
reserved
RTS
DTR
RXE
TXE
LBE
Type
R/W
RO
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
1
1
0
Description
Enable Request to Send
Value Description
1 RTS hardware flow control is enabled. Data is only requested
(by asserting U1RTS) when the receive FIFO has available
entries.
0 RTS hardware flow control is disabled.
This bit is implemented only on UART1 and is reserved for UART0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Request to Send
When RTSEN is clear, the status of this bit is reflected on the U1RTS
signal. If RTSEN is set, this bit is ignored on a write and should be ignored
on read.
This bit is implemented only on UART1 and is reserved for UART0.
Data Terminal Ready
This bit sets the state of the U1DTR output.
This bit is implemented only on UART1 and is reserved for UART0.
UART Receive Enable
Value Description
1 The receive section of the UART is enabled.
0 The receive section of the UART is disabled.
If the UART is disabled in the middle of a receive, it completes the current
character before stopping.
Note: To enable reception, the UARTEN bit must also be set.
UART Transmit Enable
Value Description
1 The transmit section of the UART is enabled.
0 The transmit section of the UART is disabled.
If the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note: To enable transmission, the UARTEN bit must also be set.
UART Loop Back Enable
Value Description
1 The UnTx path is fed through the UnRx path.
0 Normal operation.
July 24, 2012
643
Texas Instruments-Production Data