LM3S8G62 Datasheet, PDF (26/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

Table of Contents
OBSOLETE: TI has discontinued production of this device.
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 742
I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 743
I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 744
I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 745
I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 746
I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 747
I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 748
I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 749
I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 750
I²C Slave Data (I2CSDR), offset 0x808 ........................................................................... 752
I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 753
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 754
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 755
I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 756
Controller Area Network (CAN) Module ..................................................................................... 757
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 778
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 780
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 783
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 784
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 785
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 786
Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 ....................................... 788
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 789
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 789
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 790
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 790
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 793
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 793
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 794
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 794
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 796
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 796
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 797
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 797
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 799
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 799
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 802
Register 23: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 802
Register 24: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 802
Register 25: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 802
Register 26: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 802
Register 27: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 802
Register 28: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 802
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 802
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 803
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 803
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 804
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July 24, 2012
Texas Instruments-Production Data