LM3S8G62 Datasheet, PDF (178/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

System Control
OBSOLETE: TI has discontinued production of this device.
5.2
5.2.1
5.2.2
5.2.2.1
5.2.2.2
Functional Description
The System Control module provides the following capabilities:
■ Device identification, see “Device Identification” on page 178
■ Local control, such as reset (see “Reset Control” on page 178), power (see “Power
Control” on page 184) and clock control (see “Clock Control” on page 184)
■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 191
Device Identification
Several read-only registers provide software with information on the microcontroller, such as version,
part number, SRAM size, Flash memory size, and other features. See the DID0 (page 196), DID1
(page 223), DC0-DC9 (page 225) and NVMSTAT (page 247) registers.
Reset Control
This section discusses aspects of hardware functions during reset as well as system software
requirements following the reset sequence.
CMOD0 and CMOD1 Test-Mode Control Pins
Two pins, CMOD0 and CMOD1, are defined for internal use for testing the microcontroller during
manufacture. They have no end-user function and should not be used. The CMOD pins should be
connected to ground.
Reset Sources
The LM3S8G62 microcontroller has six sources of reset:
1. Power-on reset (POR) (see page 179).
2. External reset input pin (RST) assertion (see page 180).
3. Internal brown-out (BOR) detector (see page 181).
4. Software-initiated reset (with the software reset registers) (see page 182).
5. A watchdog timer reset condition violation (see page 182).
6. MOSC failure (see page 183).
Table 5-3 provides a summary of results of the various reset operations.
Table 5-3. Reset Sources
Reset Source
Power-On Reset
RST
Brown-Out Reset
Software System Request
Reset using the SYSRESREQ
bit in the APINT register.
Core Reset?
Yes
Yes
Yes
Yes
JTAG Reset?
Yes
Yes
Yes
Yes
On-Chip Peripherals Reset?
Yes
Yes
Yes
Yes
178
July 24, 2012
Texas Instruments-Production Data