LM3S8G62 Datasheet, PDF (27/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S8G62 Microcontroller
Register 33:
Register 34:
Register 35:
Register 36:
Register 37:
CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 804
CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 805
CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 805
CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 806
CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 806
Ethernet Controller ...................................................................................................................... 807
Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 ....... 821
Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 824
Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 826
Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 828
Register 5: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 830
Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 832
Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 833
Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 834
Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 836
Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 838
Register 11: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 839
Register 12: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 840
Register 13: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 841
Register 14: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 842
Register 15: Ethernet MAC LED Encoding (MACLED), offset 0x040 .................................................... 843
Register 16: Ethernet PHY MDIX (MDIX), offset 0x044 ....................................................................... 845
Register 17: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 846
Register 18: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 848
Register 19: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 850
Register 20: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 851
Register 21: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 852
Register 22: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 854
Register 23: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 856
Register 24: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 857
Register 25: Ethernet PHY Management Register 17 – Mode Control/Status (MR17), address 0x11 ...... 858
Register 26: Ethernet PHY Management Register 27 – Special Control/Status (MR27), address
0x1B ............................................................................................................................. 860
Register 27: Ethernet PHY Management Register 29 – Interrupt Status (MR29), address 0x1D ............. 861
Register 28: Ethernet PHY Management Register 30 – Interrupt Mask (MR30), address 0x1E ............... 863
Register 29: Ethernet PHY Management Register 31 – PHY Special Control/Status (MR31), address
0x1F ............................................................................................................................. 865
Analog Comparators ................................................................................................................... 866
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 871
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 872
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 873
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 874
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 875
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 875
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 876
July 24, 2012
27
Texas Instruments-Production Data