LM3S8G62 Datasheet, PDF (816/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

Ethernet Controller
OBSOLETE: TI has discontinued production of this device.
17.3.4
17.3.5
■ Energy Detect Power-Down
Power-down mode is activated by setting the PWRDN bit in the MR0 register. When the PHY is in
power-down mode, it consumes minimum power. When the PWRDN bit is cleared, the PHY powers
up and is automatically reset.
The energy detect power-down mode is activated by setting the EDPD bit in the MR17 register. In
this mode of operation, when no energy is present on the line, the PHY is powered down, except
for the managmenet interface, the SQUELCH circuit and the ENERGYON logic. The ENERGYON
logic is used to detect the presence of valid energy from 100BASE-T, 10BASE-T, or auto-negotiation
signals. While the PHY is powered down, nothing is transmitted. When link pulses or packets are
received, the PHY powers-up. The PHY automatically resets itself into the state it had prior to power
down and sets the EONIS bit in the MR29 register. The first and possibly the second packet to
activate the ENERGYON mode may be lost.
Interrupts
The Ethernet Controller can generate an interrupt for one or more of the following conditions:
■ A frame has been received into an empty RX FIFO
■ A frame transmission error has occurred
■ A frame has been transmitted successfully
■ A frame has been received with inadequate room in the RX FIFO (overrun)
■ A frame has been received with one or more error conditions (for example, FCS failed)
■ An MII management transaction between the MAC and PHY layers has completed
■ One or more of the following PHY layer conditions occurs:
– Auto-Negotiate Complete
– Remote Fault
– Link Partner Acknowledge
– Parallel Detect Fault
– Page Received
Refer to Ethernet PHY Management Register 29 - Interrupt Source Flags (MR29) (see
page 861) for additional details regarding PHY interrupts.
DMA Operation
The Ethernet peripheral provides request signals to the μDMA controller and has a dedicated channel
for transmit and one for receive. The request is a single type for both channels. Burst requests are
not supported. The RX channel request is asserted when a packet is received while the TX channel
request is asserted when the transmit FIFO becomes empty.
No special configuration is needed to enable the Ethernet peripheral for use with the μDMA controller.
Because the size of a received packet is not known until the header is examined, it is best to set
up the initial μDMA transfer to copy the first 4 words including the packet length plus the Ethernet
816
July 24, 2012
Texas Instruments-Production Data