LM3S8G62 Datasheet, PDF (1004/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

Signal Tables
OBSOLETE: TI has discontinued production of this device.
Table 22-7. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PC1
I/O
TTL
GPIO port C bit 1.
B9
SWDIO
I/O
TTL
JTAG TMS and SWDIO.
TMS
I
TTL
JTAG TMS and SWDIO.
B10
CMOD1
I
TTL
CPU Mode bit 1. Input must be set to logic 0 (grounded); other
encodings reserved.
PE2
I/O
TTL
GPIO port E bit 2.
AIN9
I
Analog Analog-to-digital converter input 9.
CCP2
B11
CCP4
I/O
TTL
Capture/Compare/PWM 2.
I/O
TTL
Capture/Compare/PWM 4.
PhA0
I
TTL
QEI module 0 phase A.
PhB1
I
TTL
QEI module 1 phase B.
PE1
I/O
TTL
GPIO port E bit 1.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
B12
CCP6
I/O
TTL
Capture/Compare/PWM 6.
Fault0
I
TTL
PWM Fault 0.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
C1
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
C2
NC
-
-
No connect. Leave the pin electrically unconnected/isolated.
VDDC
C3
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 24-6 on page 1036 .
C4
GND
-
Power Ground reference for logic and I/O pins.
C5
GND
-
Power Ground reference for logic and I/O pins.
VDDA
C6
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in Table 24-2 on page 1031 , regardless of system
implementation.
VDDA
C7
-
Power The positive supply for the analog circuits (ADC, Analog
Comparators, etc.). These are separated from VDD to minimize
the electrical noise contained on VDD from affecting the analog
functions. VDDA pins must be supplied with a voltage that meets
the specification in Table 24-2 on page 1031 , regardless of system
implementation.
C8
GND
-
Power Ground reference for logic and I/O pins.
C9
GND
-
Power Ground reference for logic and I/O pins.
C10
VDD
-
Power Positive supply for I/O and some logic.
PB2
I/O
TTL
GPIO port B bit 2.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
C11
CCP3
I2C0SCL
I/O
TTL
Capture/Compare/PWM 3.
I/O
OD
I²C module 0 clock.
IDX0
I
TTL
QEI module 0 index.
1004
Texas Instruments-Production Data
July 24, 2012