LM3S8G62 Datasheet, PDF (1056/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Register Quick Reference
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Cortex-M3 Peripherals
Memory Protection Unit (MPU) Registers
Base 0xE000.E000
MPUTYPE, type RO, offset 0xD90, reset 0x0000.0800
DREGION
IREGION
SEPARATE
MPUCTRL, type R/W, offset 0xD94, reset 0x0000.0000
MPUNUMBER, type R/W, offset 0xD98, reset 0x0000.0000
PRIVDEFEN HFNMIENA ENABLE
MPUBASE, type R/W, offset 0xD9C, reset 0x0000.0000
ADDR
MPUBASE1, type R/W, offset 0xDA4, reset 0x0000.0000
ADDR
MPUBASE2, type R/W, offset 0xDAC, reset 0x0000.0000
ADDR
MPUBASE3, type R/W, offset 0xDB4, reset 0x0000.0000
ADDR
MPUATTR, type R/W, offset 0xDA0, reset 0x0000.0000
XN
AP
SRD
MPUATTR1, type R/W, offset 0xDA8, reset 0x0000.0000
XN
AP
SRD
MPUATTR2, type R/W, offset 0xDB0, reset 0x0000.0000
XN
AP
SRD
MPUATTR3, type R/W, offset 0xDB8, reset 0x0000.0000
XN
AP
SRD
System Control
Base 0x400F.E000
DID0, type RO, offset 0x000, reset - (see page 196)
VER
MAJOR
PBORCTL, type R/W, offset 0x030, reset 0x0000.0002 (see page 198)
ADDR
ADDR
ADDR
ADDR
NUMBER
VALID
REGION
VALID
REGION
VALID
REGION
VALID
TEX
SIZE
TEX
SIZE
TEX
SIZE
TEX
SIZE
REGION
S
C
B
ENABLE
S
C
B
ENABLE
S
C
B
ENABLE
S
C
B
ENABLE
CLASS
MINOR
RIS, type RO, offset 0x050, reset 0x0000.0000 (see page 199)
BORIOR
IMC, type R/W, offset 0x054, reset 0x0000.0000 (see page 201)
MOSCPUPRIS
PLLLRIS
BORRIS
MOSCPUPIM
PLLLIM
BORIM
1056
Texas Instruments-Production Data
July 24, 2012