LM3S8G62 Datasheet, PDF (186/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

System Control
OBSOLETE: TI has discontinued production of this device.
a larger assortment of clock configuration options. These registers control the following clock
functionality:
■ Source of clocks in sleep and deep-sleep modes
■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
■ Crystal input selection
Important: Write the RCC register prior to writing the RCC2 register. If a subsequent write to the
RCC register is required, include another register access after writing the RCC register
and before writing the RCC2 register.
Figure 5-5 shows the logic for the main clock tree. The peripheral blocks are driven by the system
clock signal and can be individually enabled/disabled. When the PLL is enabled, the ADC clock
signal is automatically divided down to 16 MHz from the PLL output for proper ADC operation. The
PWM clock signal is a synchronous divide of the system clock to provide the PWM circuit with more
range (set with PWMDIV in RCC).
Note: When the ADC module is in operation, the system clock must be at least 16 MHz.
186
July 24, 2012
Texas Instruments-Production Data