LM3S8G62 Datasheet, PDF (1008/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

Signal Tables
OBSOLETE: TI has discontinued production of this device.
Table 22-7. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PC4
I/O
TTL
GPIO port C bit 4.
CCP1
I/O
TTL
Capture/Compare/PWM 1.
CCP2
I/O
TTL
Capture/Compare/PWM 2.
L1
CCP4
I/O
TTL
Capture/Compare/PWM 4.
CCP5
I/O
TTL
Capture/Compare/PWM 5.
PhA0
I
TTL
QEI module 0 phase A.
PC7
I/O
TTL
GPIO port C bit 7.
C1o
O
TTL
Analog comparator 1 output.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
L2
CCP4
I/O
TTL
Capture/Compare/PWM 4.
PhB0
I
TTL
QEI module 0 phase B.
U1Tx
O
TTL
UART module 1 transmit. When in IrDA mode, this signal has IrDA
modulation.
PA0
I/O
TTL
GPIO port A bit 0.
U0Rx
L3
I
TTL
UART module 0 receive. When in IrDA mode, this signal has IrDA
modulation.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
PA3
I/O
TTL
GPIO port A bit 3.
L4
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
SSI0Fss
I/O
TTL
SSI module 0 frame signal
PA4
I/O
TTL
GPIO port A bit 4.
L5
CAN0Rx
I
TTL
CAN module 0 receive.
SSI0Rx
I
TTL
SSI module 0 receive
PA6
I/O
TTL
GPIO port A bit 6.
CAN0Rx
I
TTL
CAN module 0 receive.
L6
CCP1
I/O
TTL
Capture/Compare/PWM 1.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
L7
RXIN
I
Analog RXIN of the Ethernet PHY.
L8
TXON
O
TTL
TXON of the Ethernet PHY.
L9
MDIO
I/O
OD
MDIO of the Ethernet PHY.
L10
GND
-
Power Ground reference for logic and I/O pins.
L11
OSC0
I
Analog Main oscillator crystal input or an external clock reference input.
VBAT
L12
-
Power Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
1008
Texas Instruments-Production Data
July 24, 2012