LM3S8G62 Datasheet, PDF (979/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S8G62 Microcontroller
Table 22-2. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PA4
I/O
TTL
GPIO port A bit 4.
30
CAN0Rx
I
TTL
CAN module 0 receive.
SSI0Rx
I
TTL
SSI module 0 receive
PA5
I/O
TTL
GPIO port A bit 5.
31
CAN0Tx
O
TTL
CAN module 0 transmit.
SSI0Tx
O
TTL
SSI module 0 transmit
32
VDD
-
Power Positive supply for I/O and some logic.
33
GND
-
Power Ground reference for logic and I/O pins.
PA6
I/O
TTL
GPIO port A bit 6.
CAN0Rx
I
TTL
CAN module 0 receive.
34
CCP1
I/O
TTL
Capture/Compare/PWM 1.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
PWM4
O
TTL
PWM 4. This signal is controlled by PWM Generator 2.
PA7
I/O
TTL
GPIO port A bit 7.
CAN0Tx
O
TTL
CAN module 0 transmit.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
35
CCP4
I/O
TTL
Capture/Compare/PWM 4.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
36
VDD
-
Power Positive supply for I/O and some logic.
37
RXIN
I
Analog RXIN of the Ethernet PHY.
VDDC
38
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in Table 24-6 on page 1036 .
39
GND
-
Power Ground reference for logic and I/O pins.
40
RXIP
I
Analog RXIP of the Ethernet PHY.
41
ERBIAS
O
Analog 12.4-kΩ resistor (1% precision) used internally for Ethernet PHY.
42
GND
-
Power Ground reference for logic and I/O pins.
43
TXOP
O
TTL
TXOP of the Ethernet PHY.
44
VDD
-
Power Positive supply for I/O and some logic.
45
GND
-
Power Ground reference for logic and I/O pins.
46
TXON
O
TTL
TXON of the Ethernet PHY.
PF0
I/O
TTL
GPIO port F bit 0.
PWM0
O
TTL
PWM 0. This signal is controlled by PWM Generator 0.
47
PhB0
I
TTL
QEI module 0 phase B.
U1DSR
I
TTL
UART module 1 Data Set Ready modem output control line.
48
OSC0
I
Analog Main oscillator crystal input or an external clock reference input.
49
OSC1
O
Analog Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
50
WAKE
I
TTL
An external input that brings the processor out of Hibernate mode
when asserted.
July 24, 2012
979
Texas Instruments-Production Data