LM3S8G62 Datasheet, PDF (7/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S8G62 Microcontroller
12.3.3 Hardware Sample Averaging Circuit ............................................................................. 541
12.3.4 Analog-to-Digital Converter .......................................................................................... 542
12.3.5 Differential Sampling ................................................................................................... 546
12.3.6 Internal Temperature Sensor ........................................................................................ 548
12.3.7 Digital Comparator Unit ............................................................................................... 549
12.4 Initialization and Configuration ..................................................................................... 553
12.4.1 Module Initialization ..................................................................................................... 553
12.4.2 Sample Sequencer Configuration ................................................................................. 554
12.5 Register Map .............................................................................................................. 554
12.6 Register Descriptions .................................................................................................. 556
13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 615
13.1 Block Diagram ............................................................................................................ 616
13.2 Signal Description ....................................................................................................... 616
13.3 Functional Description ................................................................................................. 617
13.3.1 Transmit/Receive Logic ............................................................................................... 618
13.3.2 Baud-Rate Generation ................................................................................................. 618
13.3.3 Data Transmission ...................................................................................................... 619
13.3.4 Serial IR (SIR) ............................................................................................................. 619
13.3.5 ISO 7816 Support ....................................................................................................... 620
13.3.6 Modem Handshake Support ......................................................................................... 621
13.3.7 LIN Support ................................................................................................................ 622
13.3.8 FIFO Operation ........................................................................................................... 623
13.3.9 Interrupts .................................................................................................................... 624
13.3.10 Loopback Operation .................................................................................................... 625
13.3.11 DMA Operation ........................................................................................................... 625
13.4 Initialization and Configuration ..................................................................................... 625
13.5 Register Map .............................................................................................................. 626
13.6 Register Descriptions .................................................................................................. 628
14 Synchronous Serial Interface (SSI) .................................................................... 678
14.1 Block Diagram ............................................................................................................ 679
14.2 Signal Description ....................................................................................................... 679
14.3 Functional Description ................................................................................................. 680
14.3.1 Bit Rate Generation ..................................................................................................... 680
14.3.2 FIFO Operation ........................................................................................................... 681
14.3.3 Interrupts .................................................................................................................... 681
14.3.4 Frame Formats ........................................................................................................... 682
14.3.5 DMA Operation ........................................................................................................... 689
14.4 Initialization and Configuration ..................................................................................... 690
14.5 Register Map .............................................................................................................. 691
14.6 Register Descriptions .................................................................................................. 692
15 Inter-Integrated Circuit (I²C) Interface ................................................................ 720
15.1 Block Diagram ............................................................................................................ 721
15.2 Signal Description ....................................................................................................... 721
15.3 Functional Description ................................................................................................. 721
15.3.1 I²C Bus Functional Overview ........................................................................................ 722
15.3.2 Available Speed Modes ............................................................................................... 724
15.3.3 Interrupts .................................................................................................................... 725
15.3.4 Loopback Operation .................................................................................................... 726
July 24, 2012
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