LM3S8G62 Datasheet, PDF (635/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S8G62 Microcontroller
Bit/Field
5
4
3
2
1
Name
TXFF
RXFE
BUSY
DCD
DSR
Type
RO
RO
RO
RO
RO
Reset
0
Description
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
1 If the FIFO is disabled (FEN is 0), the transmit holding register
is full.
If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
0 The transmitter is not full.
1
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
1 If the FIFO is disabled (FEN is 0), the receive holding register
is empty.
If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
0 The receiver is not empty.
0
UART Busy
Value Description
1 The UART is busy transmitting data. This bit remains set until
the complete byte, including all stop bits, has been sent from
the shift register.
0 The UART is not busy.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
0
Data Carrier Detect
Value Description
1 The U1DCD signal is asserted.
0 The U1DCD signal is not asserted.
This bit is implemented only on UART1 and is reserved for UART0.
0
Data Set Ready
Value Description
1 The U1DSR signal is asserted.
0 The U1DSR signal is not asserted.
This bit is implemented only on UART1 and is reserved for UART0.
July 24, 2012
635
Texas Instruments-Production Data