LM3S8G62 Datasheet, PDF (275/1096 Pages) Texas Instruments – Stellaris® LM3S8G62 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S8G62 Microcontroller
Register 38: Software Reset Control 2 (SRCR2), offset 0x048
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 4 (DC4) register.
Software Reset Control 2 (SRCR2)
Base 0x400F.E000
Offset 0x048
Type R/W, reset 0x00000000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved EPHY0 reserved EMAC0
reserved
Type RO
R/W
RO
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
UDMA
reserved
GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
Type RO
RO
R/W
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31
30
29
28
27:14
13
12:7
6
Name
reserved
EPHY0
reserved
EMAC0
reserved
UDMA
reserved
GPIOG
Type
RO
R/W
RO
R/W
RO
R/W
RO
R/W
Reset
0
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PHY0 Reset Control
When this bit is set, Ethernet PHY layer 0 is reset. All internal data is
lost and the registers are returned to their reset states. This bit must be
manually cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MAC0 Reset Control
When this bit is set, Ethernet MAC layer 0 is reset. All internal data is
lost and the registers are returned to their reset states. This bit must be
manually cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Micro-DMA Reset Control
When this bit is set, uDMA module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Port G Reset Control
When this bit is set, Port G module is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
July 24, 2012
275
Texas Instruments-Production Data